Central Library, Indian Institute of Technology Delhi
केंद्रीय पुस्तकालय, भारतीय प्रौद्योगिकी संस्थान दिल्ली

Transactional memory [electronic resource] / James R. Larus and Ravi Rajwar.

By: Larus, James RContributor(s): Rajwar, RaviMaterial type: TextTextSeries: Synthesis lectures on computer architecture ; #2.Publication details: San Rafael, Calif (1537 Fourth Street, San Rafael, CA 94901 USA) :: Morgan & Claypool Publishers,, 2006Edition: 1st edDescription: 1 electronic text (xiii, 211 p. : ill.) : digital fileISBN: 9781598291254 (electronic bk.); 1598291254 (electronic bk.); 1598291246 (pbk.); 9781598291247 (pbk.)Uniform titles: Synthesis digital library of engineering and computer science. Subject(s): Transactional systems (Computer systems) | Threads (Computer programs) | Syncronization | Parallel programming (Computer science) | Transactional memory | Parallel programming concurrent programming | Compilers | Programming languages | Computer architecture | Computer hardware | Wait-free data structures | Cache coherence | SynchronizationDDC classification: 005.758 LOC classification: QA76.545 | .L278 2006Online resources: Abstract with links to resource | Abstract with links to full text Also available in print.
Contents:
Introduction -- Programming transactional memory -- Software transactional memory -- Hardware-supported transactional memory -- Conclusions.
Summary: The advent of multicore processors has renewed interest in the idea of incorporating transactions into the programming model used to write parallel programs. This approach, known as transactional memory, offers an alternative, and hopefully better, way to coordinate concurrent threads. The ACI (atomicity, consistency, isolation) properties of transactions provide a foundation to ensure that concurrent reads and writes of shared data do not produce inconsistent or incorrect results. At a higher level, a computation wrapped in a transaction executes atomically either it completes successfully and commits its result in its entirety or it aborts. In addition, isolation ensures the transaction produces the same result as if no other transactions were executing concurrently. Although transactions are not a parallel programming panacea, they shift much of the burden of synchronizing and coordinating parallel computations from a programmer to a compiler, runtime system, and hardware. The challenge for the system implementers is to build an efficient transactional memory infrastructure. This book presents an overview of the state of the art in the design and implementation of transactional memory systems, as of early summer 2006.
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Mode of access: World Wide Web.

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Part of: Synthesis digital library of engineering and computer science.

Series from website.

Includes bibliographical references.

Introduction -- Programming transactional memory -- Software transactional memory -- Hardware-supported transactional memory -- Conclusions.

Abstract freely available; full-text restricted to subscribers or individual document purchasers.

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The advent of multicore processors has renewed interest in the idea of incorporating transactions into the programming model used to write parallel programs. This approach, known as transactional memory, offers an alternative, and hopefully better, way to coordinate concurrent threads. The ACI (atomicity, consistency, isolation) properties of transactions provide a foundation to ensure that concurrent reads and writes of shared data do not produce inconsistent or incorrect results. At a higher level, a computation wrapped in a transaction executes atomically either it completes successfully and commits its result in its entirety or it aborts. In addition, isolation ensures the transaction produces the same result as if no other transactions were executing concurrently. Although transactions are not a parallel programming panacea, they shift much of the burden of synchronizing and coordinating parallel computations from a programmer to a compiler, runtime system, and hardware. The challenge for the system implementers is to build an efficient transactional memory infrastructure. This book presents an overview of the state of the art in the design and implementation of transactional memory systems, as of early summer 2006.

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